This document defines the design, fabrication, and validation requirements for a High-Density Interconnect (HDI) Rigid-Flex PCB. The component serves as the primary interconnect between a high-resolution CMOS Image Sensor (CIS) and the host logic board.
Primary Function: Transmission of high-speed MIPI CSI-2/C-PHY differential signals.
Key Constraints:
- Micro-via Technology: 2+N+2 or Anylayer HDI structure.
- Signal Integrity: Support for >2.5 Gbps/lane data rates.
- Mechanical Reliability: Dynamic bending endurance >100,000 cycles.
MATERIAL & STACK-UP SPECIFICATIONS
To address the Flex-to-Rigid transition and impedance control, the material selection is critical.
Layer Build-up (Structure: 4-Layer Rigid-Flex)
- Structure Type: 2R + 2F + 2R (Air-gap construction preferred for flexibility).
- Rigid Material: High-Tg FR-4 (Tg > 170°C), Low-Loss/Halogen-Free.
- Flex Material (Critical):
- Base: Adhesiveless Polyimide (PI). Adhesive-based substrates are strictly prohibited due to via reliability issues.
- Copper: Rolled Annealed (RA) Copper for flex layers (Grain direction parallel to signal path). Electro-Deposited (ED) Copper is permitted for outer rigid layers only.
- Coverlay: Polyimide Coverlay (12.5µm PI + 15µm Adhesive).
Stack-up Example (Total Thickness: 0.35mm ± 10%)
| Layer | Type | Material | Function | Note |
| L1 | Conductor | Copper (12µm + Plating) | Component/Pad | Rigid |
| P1 | Dielectric | Prepreg (106/1080) | Dielectric | Rigid |
| L2 | Conductor | Copper (12µm) | GND Plane | Rigid |
| C1 | Adhesive | Acrylic/Epoxy | Bondply | No-Flow Prepreg |
| L3 | Conductor | RA Copper (12µm) | MIPI Signals | Flex Core |
| D1 | Dielectric | Polyimide (25µm) | Core Dielectric | Flex Core |
| L4 | Conductor | RA Copper (12µm) | GND/Power | Flex Core |
| C2 | Adhesive | Acrylic/Epoxy | Bondply | No-Flow Prepreg |
| L5 | Conductor | Copper (12µm) | Power Plane | Rigid |
| P2 | Dielectric | Prepreg (106/1080) | Dielectric | Rigid |
| L6 | Conductor | Copper (12µm + Plating) | Component/Pad | Rigid |
MICRO-VIA & HDI TECHNOLOGY PROCESS
To address the Micro-via HDI Process challenge:
Via Architecture
- Blind Vias: Laser drilled, L1-L2 and L6-L5.
- Diameter: 0.10mm (4 mil).
- Capture Pad: 0.25mm.
- Buried Vias: Mechanical drilled, L2-L5 (Through the Flex Core).
- Plating:
- Blind vias must be Copper Filled (Via-in-Pad capable) to ensure flat surface for Wire Bonding or CSP mounting.
- Wrap-plating thickness meets IPC-6013 Class 3 requirements.
Laser Drilling Process Control
- Desmear: Plasma cleaning (O2/CF4 plasma) is mandatory post-laser drilling to remove carbonization from the Polyimide surface before plating.
- Registration: Laser drill alignment accuracy must be within ±15µm relative to the L2/L5 pads.
MECHANICAL DESIGN & BENDING CONTROL
To address Bend-radius control and Flex-to-Rigid transition:
Bending Area Design Rules
- Neutral Axis Construction: The high-speed signal layer (L3) must be positioned at the mechanical neutral axis of the flex stack-up to minimize tensile/compressive stress during bending.
- Trace Geometry:
- Traces in the bend area must run perpendicular (90°) to the bend axis.
- NO VIAS are permitted in the dynamic bending zone.
- I-Beam prevention: L3 and L4 conductors must be staggered (offset) to effectively retain flexibility; do not stack copper directly on top of copper.
Transition Zone (Rigid-to-Flex)
- Teardrops: All trace-to-pad connections in the transition zone must utilize teardrops to prevent stress concentration.
- Coverlay Opening: The coverlay termination must overlap into the rigid section by at least 0.2mm.
- Stiffener Strategy:
- Use a graduated stiffener approach or ensure the PI stiffener ends 0.5mm away from the rigid board edge to avoid a rigorous stress point (Stress Concentration Point).
- Epoxy strain relief (UV Glue) is required at the rigid-flex interface.
SIGNAL INTEGRITY (HIGH-SPEED ROUTING)
To address the High-Speed Signal requirement:
MIPI CSI-2 Routing Guidelines
- Impedance Profile:
- Differential Impedance: 100Ω±10%100Ω±10% (or 85Ω85Ω depending on PHY spec).
- Single-ended Impedance: 50Ω±10%50Ω±10%.
- Ground Reference: All high-speed traces on L3 must reference a solid GND plane on L4. Cross-hatched copper on L4 is permitted for flexibility but hatch pitch must be <λ/20<λ/20 of the highest frequency (approx 0.1mm pitch).
- EMI Shielding: Application of Silver Paste Shielding Film (EMI Film) on the outer layers of the flex area is required to prevent crosstalk and radiated emissions.
RELIABILITY TESTING & QUALIFICATION
To address Mechanical Reliability Testing:
The manufactured lots must undergo the following qualification tests based on IPC-TM-650 standards.
| Test Item | Condition | Pass Criteria |
| MIT (Mechanical Impulse Test) | Bend Radius: 1.5mm1.5mm (or 10×10× flex thickness)<br>Speed: 60 cycles/min<br>Angle: ±90∘±90∘ | >100,000>100,000 Cycles<br>Resistance Change <10%<10% |
| Thermal Shock | −40∘C−40∘C to +125∘C+125∘C, 30 min dwell, 500 cycles | No Delamination<br>Via connectivity verified |
| Interconnect Stress Test (IST) | Simulates multiple reflow cycles (260∘C260∘C) | No barrel cracks in Micro-vias |
| Peel Strength | Coverlay to Copper / Stiffener to Flex | >0.8N/mm>0.8N/mm |
| CAF Testing | Conductive Anodic Filament growth check | High resistance maintained |
MANUFACTURING DELIVERABLES (DFM)
The following data package is required for fabrication:
- ODB++ or Gerber X2 files: Including specific layers for Coverlay, Stiffener (SUS/FR4), and EMI film.
- IPC-356 Netlist: For electrical Open/Short testing.
- Fab Drawing: Must specify:
- Grain direction of RA Copper.
- Definition of “Air-Gap” vs “Bonded” areas.
- Impedance coupons design for TDR testing.
