DDR4 Timing Parameters and Standards
DDR4 SDRAM timing and signal integrity (SI) must be checked both by simulation and by lab measurements. The JEDEC DDR4 standard (JESD79-4) defines key timing parameters (tRCD, tRP, tRAS, CAS latency, etc.) and electrical limits.
Simulation and Measurement Methods
In practice, engineers use simulation tools (IBIS/SPICE models, HyperLynx, Cadence Sigrity, etc.) and bench equipment (oscilloscope with DDR probes, logic analyzers, and signal interposers) to verify that real hardware meets the specs.
Key DDR4 Timing Parameters
CAS Latency (CL)
Delay (in clock cycles) between issuing a READ command and the first data bit appearing. It is programmed in the mode register. For example, CL=16 means 16 clock cycles from READ to data.
tRCD (Row-to-Column Delay)
Delay from an ACTIVATE (open row) command to a READ/WRITE command. It is the minimum time to wait after opening a row before accessing data in that row. (JEDEC tables show tRCD ≈13.5 ns for DDR4-2400.)
tRP (Row Precharge Time)
Time from a PRECHARGE command (close row) to the next ACTIVATE. It is the minimum idle time to precharge a bank. For DDR4-2400, tRP is also about 13.5 ns (same as tRCD).
tRAS (Active Time)
Minimum time between ACTIVATE (open) and PRECHARGE (close) on the same bank. It ensures data is safely written. JEDEC specifies tRAS = 32 clock cycles or more (roughly ≥ 32 ns) for DDR4-2400.
Other Parameters
DDR4 also uses parameters like tRC = tRAS + tRP (minimum cycle), tRRD, tFAW, etc. All these are defined in JESD79-4. Table cells or SPD bytes in a DIMM contain these values.
A properly equipped scope can be triggered on memory read/write bursts and measure these intervals against JEDEC requirements.
Simulation-Based Verification
Channel and Device Modeling
Simulation allows pre-layout and post-layout checking of DDR4 timing and SI. Engineers build a channel model (PCB traces, vias, package RLC) and use device models (vendor IBIS or SPICE). For example, IBIS models for the FPGA and DRAM can be generated or downloaded, with per-pin RLC for package effects. Simulations then drive DDR4 command/address sequences and data patterns.
Obtaining Models
Use memory-vendor IBIS files (derived from SPICE device models) and FPGA IBIS models (with package info). Ensure channel traces have correct impedance and spacing in the simulator.
Pre-Layout Simulation
Before routing, run ideal or approximate simulations to choose terminations and predict timing margins. Include series resistors, on-die termination (ODT), etc. Check waveforms for overshoot and reflections.
Post-Layout Simulation
After PCB layout, use extracted routing (S-parameters or RLC netlists). Simulate read and write bursts and capture waveforms at the receiver. Generate eye diagrams by sampling bits over many cycles (often using a “Data Eye” function in tools). Verify the setup/hold margin by measuring the eye opening at the receiver threshold (often ±70 mV around VREF). Ensure the simulated eye meets the JEDEC mask.
Timing Analysis
Use Static Timing Analysis (STA) with timing constraints for the DDR PHY. The goal is to confirm that signals meet tCK, tRCD, tRP, tRAS, etc. For training and calibration paths, STA can analyze the full delay path including FPGA, package, and DRAM latencies.
Tools like Cadence Sigrity or Mentor HyperLynx can include power and crosstalk effects.
For example, these tools can simulate worst-case crosstalk noise from adjacent lines and show its impact on the data. If simulations show timing margins violate spec, the design or memory timing must be adjusted.
Measurement-Based Verification
Oscilloscope
A digital scope with ≥10 GHz analog bandwidth is recommended (DDR4-3200 has ~1600 MHz data rate). The scope needs DDR compliance or SI software (e.g. Tektronix MSO/DPO70000 with DDRA, or Keysight Infiniium).
Probes and Signal Access
Use high-speed differential probes for DQ/DQS lines and single-ended probes for command/address. Accessing signals on a DRAM DIMM can be challenging. Often a signal interposer PCB is placed between the controller and DRAM; it “picks off” signals at the module edges for probes. Alternate methods include a DRAM socket breakout or dedicated DDR probe heads. Model the probe’s effect (impedance) and use the scope’s de-embedding feature if available.
Triggering
Configure the scope to trigger on DDR read/write bursts. One method is a window trigger on DQ or DQS: set a voltage window that catches the preamble of a burst. Another is a graphical trigger (on Tektronix scopes) set over the expected waveform. Using DQS as the timing reference (clock strobe) is common: trigger on a DQS edge so that DQ eye is aligned. The oscilloscope should separate read and write windows in the capture.
Measurement Procedure
After triggering on a burst, use the scope’s eye-diagram function. Align the captured bits and overlay them to form an eye. Measure the eye height and width at the receiver threshold (typically ±70 mV around VREF). Also measure rise/fall times and skew between lines. Use the scope’s DDR compliance mode or mask tests to automate pass/fail versus JEDEC masks.
Oscilloscope Bandwidth
Choose bandwidth ~2–3× the data rate. For DDR4-2400 (12 Gb/s), at least 20–30 GHz is ideal, but practical rules often use a 3× factor. High-end scopes (e.g. 20–33 GHz) improve accuracy for eye measurement.
Setup Summary
Connect probes carefully and calibrate (deskew the channels). Apply test patterns (e.g. pseudo-random PRBS or checkerboard) to stress SI. Use a termination strategy (series/parallel) matching the design. Begin by capturing DQ eyes; verify that the measured tRCD, tRP, tRAS (by measuring time between ACT and data, etc.) meet expected values. If violations occur, check for SI issues (reflections, crosstalk) or adjust memory timings.
Signal Integrity Analysis
After capturing waveforms, analyze SI phenomena:
Eye Diagrams
The eye opening shows combined effects of jitter, ISI, and noise. A wide, clear eye means good SI. Look at the eye height (voltage margin) and eye width (time margin). Use the scope’s measurement cursors or mask test to quantify eye width at VREF. The eye diagram for the DDR4 data bus is created by overlaying many data bits (with read/write bursts separated). Ensuring the eye fully opens at ±70 mV (for the input threshold) is a common criterion.
Reflections (Impedance Mismatch)
Check for ringing or overshoot in the single-shot waveform. These are signs of reflections due to discontinuities (via stubs, connector impedance, or probes). Proper termination (series or parallel) should minimize reflections. On the scope, reflections look like extra “echoes” after the main edge. If significant ringing is seen, revise terminations or routing to smooth impedance. When measuring, probe near the receiver end; probing at the source may show false reflections.
Crosstalk
Crosstalk is interference from adjacent switching lines. In DDR4, switching address/command or neighboring DQ lines can inject noise. To detect crosstalk, capture data while toggling one “aggressor” signal and observe a “victim” line. The Keysight case shows that when adjacent address lines switch, the victim line’s eye degrades. In practice, you may disable ODT or push aggressor toggling patterns to highlight crosstalk. If crosstalk is high, increase spacing, add shielding, or use stronger termination.
Jitter and Noise
Use the eye diagram to estimate timing jitter (horizontal closure) and voltage noise (vertical closure). Many scopes have jitter/noise analysis tools. Ensure that worst-case jitter keeps the data sampling point within the eye. DDR4 has tight margins, so even tens of picoseconds of jitter can matter.
Compliance Tests
Beyond custom analysis, DDR4 compliance test software (Rohde & Schwarz, Keysight, Tektronix) can run standardized tests: check DDR groups against mask and timing spec. These automate eye scans, jitter tests, and bit-error-rate tests. They reference JESD79-4 limits and calculate margins.
In all measurements, compare results to JEDEC JESD79‑4 specifications. For example, verify that measured tRCD and tRP match the programmed values, and that DQ capture timing meets CL and tDQS timing requirements. Properly set up and interpreted, eye diagrams and SI measurements reveal if the DDR4 interface will reliably meet its timing budget.
